Datasheet
TYPICAL CHARACTERISTICS
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
Table of Graphs
Figure 1 ,
V
IO
Input offset voltage Distribution Figure 2 ,
Figure 3
I
IO
Input offset current vs Free-air temperature Figure 4
vs Common-mode input voltage Figure 5
I
IB
Input bias current
vs Free-air temperature Figure 6
vs Supply voltage Figure 7
vs Free-air temperature Figure 8
V
OM+
Maximum positive peak output voltage
vs Output current Figure 9
vs Settling time Figure 11
vs Supply voltage Figure 7
vs Free-air temperature Figure 8
V
OM –
Maximum negative peak output voltage
vs Output current Figure 10
vs Settling time Figure 11
V
O(PP)
Maximum peak-to-peak output voltage vs Frequency Figure 12
V
OH
High-level output voltage vs Output current Figure 13
V
OL
Low-level output voltage vs Output current Figure 14
Phase shift vs Frequency Figure 15
vs Frequency Figure 15
A
VD
Large-signal differential voltage amplification
vs Free-air temperature Figure 16
z
o
Closed-loop output impedance vs Frequency Figure 17
I
OS
Short-circuit output current vs Free-air temperature Figure 18
vs Frequency Figure 19
CMRR Common-mode rejection ratio
vs Free-air temperature Figure 20
vs Frequency Figure 21
k
SVR
Supply-voltage rejection ratio
vs Free-air temperature Figure 22
vs Supply voltage Figure 23
I
CC
Supply current
vs Free-air temperature Figure 24
V
n
Equivalent input noise voltage vs Frequency Figure 25
V
n
Input noise voltage Over a 10-second period Figure 26
I
n
Noise current vs Frequency Figure 27
THD+N Total harmonic distortion plus noise vs Frequency Figure 28
vs Free-air temperature Figure 29
SR Slew rate
vs Load capacitance Figure 30
Noninverting large signal vs Time Figure 31
Pulse response Inverting large signal vs Time Figure 32
Small signal vs Time Figure 33
B
1
Unity-gain bandwidth vs Load capacitance Figure 34
Gain margin vs Load capacitance Figure 35
φ
m
Phase margin vs Load capacitance Figure 36
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