Datasheet

  
  
µ  

SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 4
TLE2061
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
43210−1−2−3−4
V
IO
− Input Offset Voltage − mV
Percentage of Amplifiers − %
0
5
10
15
P Package
T
A
= 25°C
V
CC±
= ±15 V
736 Amplifiers Tested From 3 Wafer Lots
Figure 5
V
IO
− Input Offset Voltage − mV
10
5
0
− 2 −1 0 1
Percentage of Amplifiers − %
TLE2062
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
234
15
1836 Amplifiers Tested From 1 Wafer Lot
V
CC±
= ±15 V
T
A
= 25°C
P Package
−3−4
Figure 6
TLE2064
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
20
15
10
5
N Package
T
A
= 25°C
V
CC±
= ±15 V
86420−2−4−6−8
V
IO
− Input Offset Voltage − mV
Percentage of Amplifiers − %
0
2792 Amplifiers Tested From 2 Wafer Lots
Figure 7
− Input Bias Current − nA
I
IB
1.5
1
0.5
T
A
= 25°C
V
ID
= 0
V
CC±
= ±15 V
V
IC
− Common-Mode Input Voltage − V
−20 −15 −10 −5 0 5 10 15 20
2
0
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE