Datasheet

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  
µ  

SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2062Y electrical characteristics at V
CC±
= ±15 V, T
A
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2062Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IO
Input offset voltage 0.9 4 mV
α
VIO
Input offset voltage long-term drift (see Note 4)
V
IC
= 0,
R
S
= 50 Ω
0.04 µV/mo
I
IO
Input offset current
V
IC
= 0, R
S
= 50 Ω
2 pA
I
IB
Input bias current 4 pA
−11
−12
V
ICR
Common-mode input voltage range
−11
to
−12
to
V
V
ICR
Common-mode input voltage range
to
13
to
16
V
V
OM+
Maximum positive peak output voltage swing
R
L
= 10 kΩ 13.2 13.7
V
V
OM+
Maximum positive peak output voltage swing
R
L
= 600 Ω
12.5 13.2
V
V
OM−
Maximum negative peak output voltage swing
R
L
= 10 kΩ −13.2 −13.7
V
V
OM−
Maximum negative peak output voltage swing
R
L
= 600 Ω
−12.5 −13
V
V
O
= ±10 V, R
L
= 10 kΩ 30 230
A
VD
Large-signal differential voltage amplification
V
O
= 0 to 8 V,
R
L
= 600 Ω 25 100
V/mV
A
VD
Large-signal differential voltage amplification
V
O
= 0 to −8 V, R
L
= 600 Ω 3 25
V/mV
r
i
Input resistance 10
12
Ω
c
i
Input capacitance 4 pF
z
o
Open-loop output impedance I
O
= 0 560 Ω
CMRR Common-mode rejection ratio V
IC
= V
ICR
min, R
S
= 50 Ω 72 90 dB
k
SVR
Supply-voltage rejection ratio (∆V
CC
/∆V
IO
)
V
CC±
=
±
5 V to
±
15 V,
75
93
dB
k
SVR
Supply-voltage rejection ratio (∆V
CC
/∆V
IO
)
V
CC±
= ±5 V to ±15 V,
R
S
= 50 Ω
75 93 dB
I
CC
Supply current V
O
= 0, No load 625 690 µA
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T
A
= 150°C extrapolated
to T
A
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2062Y operating characteristics at V
CC±
= ±15 V, T
A
= 25°C
PARAMETER
TEST CONDITIONS
TLE2062Y
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
SR Slew rate at unity gain (see Figure 1) R
L
= 10 kΩ, C
L
= 100 pF 2.6 3.4 4 V/µs
V
n
Equivalent input noise voltage (see Figure 2)
f = 10 Hz, R
S
= 20 Ω 70
nV/√Hz
V
n
Equivalent input noise voltage (see Figure 2)
f = 1 kHz,
R
S
= 20 Ω 40
nV/√Hz
V
N(PP)
Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 1.1 µV
I
n
Equivalent input noise current f = 1 Hz 1.1 fA/√Hz
THD Total harmonic distortion
V
O(PP)
= 2 V,
A
VD
= 2,
R
L
= 10 kΩ,
f = 10 kHz
0.025%
B
1
Unity-gain bandwidth (see Figure 3)
R
L
= 10 kΩ, C
L
= 100 pF 2
MHz
B
1
Unity-gain bandwidth (see Figure 3)
R
L
= 600 Ω,
C
L
= 100 pF 1.5
MHz
Settling time
0.1% 5
s
Settling time
0.01%
10
µs
B
OM
Maximum output-swing bandwidth A
VD
= 1, R
L
= 10 kΩ 40 kHz
φ
m
Phase margin at unity gain (see Figure 3)
R
L
= 10 kΩ, C
L
= 100 pF 60°
φ
m
Phase margin at unity gain (see Figure 3)
R
L
= 600 Ω, C
L
= 100 pF 70°