Datasheet
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
+
−
R11
5 kΩ
A2
V
OA
DACB
R6
20 kΩ
(see Note B)
V
OB
+
−
AGND
A1
DGND
A4
R3
(see Note A)
R1
(see Note A)
AGND
+
−
C1
(see Note C)
C2
(see Note C)
R2 (see Note A)
R4 (see Note A)
+
−
AGND
OUTB
RFBB
AGND
OUTA
5
V
DD
17
7
14
DACA
/
DACB
DB0
DB7
88
88
REFB
RFBA
DACA
CS
WR
16
15
6
A3
R10
20 kΩ
(see Note B)
Latch
Input
Buffer
Control
Logic
Latch
R8
20 kΩ
R7
10 kΩ
(see Note B)
R9
10 kΩ
(see Note B)
R11
5 kΩ
R5
20 kΩ
V
I(A)
± 10 V
V
I(B)
± 10 V
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for
V
OA
= 0V with code 10000000 in DACA latch. Adjust R3 for V
OB
= 0V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10pF to 15pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
ANALOG OUTPUT
DAC LATCH CONTENTS
ANALOG OUTPUT
MSB LSB
†
ANALOG OUTPUT
MSB LSB
‡
ANALOG OUTPUT
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
−V
I
(255/256)
−V
I
(129/256)
−V
I
(128/256) = −V
i
/2
−V
I
(127/256)
−V
I
(1/256)
−V
I
(0/256) = 0
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
I
(127/128)
V
I
(1/128)
0V
−V
I
(1/128)
−V
I
(127/128)
−V
I
(128/128)
†
1LSB = (2
−8
)V
I
‡
1LSB = (2
−7
)V
I