Datasheet

TLC7225C, TLC7225I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109B – OCTOBER 1996 – REVISED FEBRUARY 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
microprocessor interface
Figures 14, 15, 16, and 17 show the hardware interface to some of the standard processors.
Address
Decode
A0
A1
LDAC
WR
DB7
DB0
Latch
EN
TLC7225
†
A15
A8
WR
ALE
AD7
AD0
8085/8088
Address Bus
Address Data Bus
†
Linear circuitry omitted for clarity
Figure 14. TLC7225 to 8085A/8088 Interface, Double-Buffered Mode
Address
Decode
A0
A1
LDAC
WR
DB7
DB0
TLC7225
†
A15
A8
R/W
AD7
AD0
8085/8088
Address Bus
Data Bus
†
Linear circuitry omitted for clarity
E or φ2
EN
Figure 15. TLC7225 to 6809/6502 Interface, Single-Buffered Mode