Datasheet

TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
data interface (continued)
CLK
DATA
LOAD
LDAC
DAC Update
A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
t
su(DATA-CLK)
t
v(DATA-CLK)
t
w(LDAC)
t
su(LOAD–LDAC)
Figure 2. LDAC-Controlled Update
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
A2
Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
A2
Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word
Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A2 A1 A0 DAC UPDATED
0 0 0 DACA
0 0 1 DACB
0 1 0 DACC
0 1 1 DACD
1 0 0 DACE
1 0 1 DACF
1 1 0 DACG
1 1 1 DACH