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BUFFER AMPLIFIER
EXTERNAL REFERENCE
LOGIC INTERFACE
SERIAL CLOCK AND UPDATE RATE
f
(SCLK)max
+
1
t
w
ǒ
CH
Ǔ
) t
w
ǒ
CL
Ǔ
t
p(CS)
+ 16
ǒ
t
w
ǒ
CH
Ǔ
) t
w
ǒ
CL
Ǔ
Ǔ
) t
w
ǒ
CS
Ǔ
SERIAL INTERFACE
10 Data Bits x x
12 Bits
MSB LSB 2 Extra (Sub-LSB) Bits
x = don’t care
10 Data Bits x x
16 Bits
MSB LSB 2 Extra (Sub-LSB) Bits
4 Upper Dummy Bits
x = don’t care
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2k Ω load with a 100pF load
capacitance. Settling time is 12.5 µ s typical to within 0.5LSB of final value.
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10M Ω and the REFIN input capacitance is typically 5pF independent of input
code. The reference voltage determines the DAC full-scale output.
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves
the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic
levels.
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:
or approximately 14MHz. The digital update rate is limited by the chip-select period, which is:
and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5 µ s limits
the update rate to 80kHz for full-scale input step transitions.
When chip select ( CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The rising edge of the SLCK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be
clocked into the input register. All CS transitions should occur when the SCLK input is low.
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data
sequence with the MSB first can be used as shown in Figure 10 :
Figure 10. 12-Bit Input Data Sequence
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
Figure 11. 16-Bit Input Data Sequence
9
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