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OPERATING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
t
h(CSH0)
t
su(CSS)
t
w(CH)
t
w(CL)
t
h(CSH1)
t
su(CS1)
t
w(CS)
t
pd(DOUT)
CS
SCLK
DIN
DOUT
t
su(DS)
t
h(DH)
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
See Note A See Note A
See Note B
MSB LSB
B. Data input from preceeding conversion cycle.
See Note C
Previous LSB
C. Sixteenth SCLK falling edge
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
over recommended operating free-air temperature range, V
DD
= 5V ± 5%, V
ref
= 2.048V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
C
L
= 100pF,
SR Output slew rate R
L
= 10k Ω , 0.3 0.5 V/ µ s
T
A
= +25 ° C
To 0.5LSB,
t
s
Output settling time C
L
= 100pF,
(1)
12.5 µ s
R
L
= 10k Ω ,
Glitch energy DIN = All 0s to all 1s 5 nV-s
REFERENCE INPUT (REFIN)
Reference feedthrough REFIN = 1V
PP
at 1kHz + 2.048Vdc
(2)
–80 dB
Reference input
REFIN = 0.2V
PP
+ 2.048Vdc 30 kHz
bandwidth (f–3dB)
(1) Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of 000
hex to 3FF hex or 3FF hex to 000 hex.
(2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref
input = 2.048Vdc + 1V
pp
at 1kHz.
Figure 1. Timing Diagram
5
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