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VOLTAGE OUTPUT (OUT)
DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1 )
OUTPUT SWITCHING CHARACTERISTICS
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Voltage output range R
L
= 10k Ω 0 V
DD
–0.4 V
Output load regulation accuracy V
O(OUT)
= 2V, R
L
= 2k Ω 0.5 LSB
I
OSC
Output short circuit current OUT to V
DD
or AGND 20 mA
V
OL(low)
Output voltage, low-level I
O(OUT)
≤ 5mA 0.25 V
V
OH(high)
Output voltage, high-level I
O(OUT)
≤ – 5mA 4.75 V
REFERENCE INPUT (REFIN)
V
I
Input voltage 0 V
DD
–2 V
r
i
Input resistance 10 M Ω
C
i
Input capacitance 5 pF
DIGITAL INPUTS (DIN, SCLK, CS)
V
IH
High-level digital input voltage 2.4 V
V
IL
Low-level digital input voltage 0.8 V
I
IH
High-level digital input current V
I
= V
DD
± 1 µ A
I
IL
Low-level digital input current V
I
= 0 ±1 µ A
C
i
Input capacitance 8 pF
DIGITAL OUTPUT (DOUT)
V
OH
Output voltage, high-level I
O
= –2mA V
DD
–1 V
V
OL
Output voltage, low-level I
O
= 2mA 0.4 V
POWER SUPPLY
V
DD
Supply voltage 4.5 5 5.5 V
V
DD
= 5.5V, No load,
V
ref
= 0 150 250 µ A
All inputs = 0V or V
DD
I
DD
Power supply current
V
DD
= 5.5V, No load,
V
ref
= 2.048V 230 350 µ A
All inputs = 0V or V
DD
ANALOG OUTPUT DYNAMIC PERFORMANCE
V
ref
= 1V
PP
at 1kHz + 2.048Vdc,
Signal-to-noise + distortion, S/(N+D) 60 dB
code = 11 1111 1111
(1)
(1) The limiting frequency value at 1V
PP
is determined by the output-amplifier slew rate.
PARAMETER MIN NOM MAX UNIT
t
su(DS)
Setup time, DIN before SCLK high 45 ns
t
h(DH)
Hold time, DIN valid after SCLK high 0 ns
t
su(CSS)
Setup time, CS low to SCLK high 1 ns
t
su(CS1)
Setup time, CS high to SCLK high 50 ns
t
h(CSH0)
Hold time, SCLK low to CS low 1 ns
t
h(CSH1)
Hold time, SCLK low to CS high 0 ns
t
w(CS)
Pulse duration, minimum chip select pulse width high 20 ns
t
w(CL)
Pulse duration, SCLK low 25 ns
t
w(CH)
Pulse duration, SCLK high 25 ns
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
pd(DOUT)
Propagation delay time, DOUT C
L
= 50pF 50 ns
4
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