Datasheet
TLC555, TLC555Y
LinCMOS TIMERS
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
0.1 µF
0.1 µF
C
T
C
L
R
L
Output
R
B
R
A
GND
TRIG
THRES
RESET
DISCH
CONT V
DD
OUT
V
DD
2/3 V
DD
1/3 V
DD
GND
t
PHL
t
PLH
t
c(H)
t
c(L)
CIRCUIT
TRIGGER
AND
THRESHOLD
VOLTAGE
WAVEFORM
TLC555
6
1
3
85
4
7
2
Pin
numbers
shown
are
for
all
packages
except
the
FK
package.
Figure 3. Astable Operation
Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C
T
charges through R
A
and R
B
to the threshold voltage level (approximately 0.67 V
DD
) and then discharges through R
B
only to the value of the trigger voltage level (approximately 0.33 V
DD
). The output is high during the charging cycle
(t
c(H)
) and low during the discharge cycle (t
c(L)
). The duty cycle is controlled by the values of R
A
, R
B
, and C
T
as shown
in the equations below.
t
c(H)
C
T
(R
A
R
B
)In2 (In2 0.693)
t
c(L)
C
T
R
B
In 2
Period t
c(H)
t
c(L)
C
T
(R
A
2R
B
)In2
Output driver duty cycle
t
c(L)
t
c(H)
t
c(L)
1–
R
B
R
A
2R
B
Output waveform duty cycle
t
c(H)
t
c(H)
t
c(L)
R
B
R
A
2R
B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH.
These delay times add directly to the period and create differences between calculated and actual values that
increase with frequency. In addition, the internal on-state resistance r
on
during discharge adds to R
B
to provide
another source of timing error in the calculation when R
B
is very low or r
on
is very high.