Datasheet

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SLAS105D − JANUARY 1995 − REVISED APRIL 2004
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2
functional block diagram
Lower Sampling
Comparators
(4 Bit)
Lower Encoder
(4 Bit)
Lower Data
Latch
Lower Sampling
Comparators
(4 Bit)
Lower Encoder
(4 Bit)
Upper Sampling
Comparators
(4 Bit)
Upper Encoder
(4 Bit)
Upper Data
Latch
Clock
Generator
OE
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
CLK
REFB
REFT
REFBS
AGND
AGND
ANALOG IN
V
DDA
REFTS
270 Ω
NOM
80 Ω
NOM
320 Ω
NOM
Resistor
Reference
Divider
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
V
DDA
AGND
ANALOG IN
EQUIVALENT OF EACH DIGITAL INPUT
V
DDD
DGND
OE, CLK
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDD
DGND
D1−D8