Datasheet

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at V
DD
= 5 V, V
REFT
= 2.5 V, V
REFB
= 0.5 V, f
(CLK)
= 20 MHz, T
A
= 25°C (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
Maximum conversion rate
TLC5510
f
I
= 1 kHz ram
p
V
I(ANLG)
= 0.5 V – 2.5 V 20 MSPS
f
conv
Maximum
conversion
rate
TLC5510A
f
I
=
1
-
kHz
ramp
V
I(ANLG)
= 0 V – 4 V 20 MSPS
BW Analog input bandwidth At – 1 dB 14 MHz
t
d(D)
Digital output delay time C
L
≤ 10 pF (see Note 1 and Figure 1) 18 30 ns
Differential gain
NTSC 40 Institute of Radio En
g
ineers (IRE)
1%
Differential phase
g()
modulation wave, f
conv
= 14.3 MSPS
0.7 degrees
t
AJ
Aperture jitter time 30 ps
t
d(s)
Sampling delay time 4 ns
t
en
Enable time, OE↓ to valid data C
L
= 10 pF 5 ns
t
dis
Disable time, OE↑ to high impedance C
L
= 10 pF 7 ns
In
p
ut tone = 1 MHz
T
A
= 25°C 45
Input
tone
=
1
MHz
Full range 43
In
p
ut tone = 3 MHz
T
A
= 25°C 45
S
p
urious free dynamic range (SFDR)
Input
tone
=
3
MHz
Full range 46
dB
Spurious
free
dynamic
range
(SFDR)
In
p
ut tone = 6 MHz
T
A
= 25°C 43
dB
Input
tone
=
6
MHz
Full range 42
In
p
ut tone = 10 MHz
T
A
= 25°C 39
Input
tone
=
10
MHz
Full range 39
SNR
Signal to noise ratio
T
A
= 25°C 46
dB
SNR
Signal
-
to
-
noise
ratio
Full range 44
dB
NOTE 1: C
L
includes probe and jig capacitance.
N
N+1
N+2
N+3
N+4
N–3N–2N–1NN+1
t
d(D)
CLK (clock)
ANALOG IN
(input signal)
D1–D8
(output data)
t
w(H)
t
w(L)
t
d(s)
Figure 1. I/O Timing Diagram