Datasheet

TLC540I, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
TLC540 TLC541
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
Supply voltage, V
CC
4.75 5 5.5 4.75 5 5.5 V
Positive reference voltage, V
ref+
(see Note 2) 2.5 V
CC
V
CC
+0.1 2.5 V
CC
V
CC
+0.1 V
Negative reference voltage, V
ref–
(see Note 2) –0.1 0 2.5 – 0.1 0 2.5 V
Differential reference voltage, V
ref+
– V
ref–
(see Note 2) 1 V
CC
V
CC
+0.2 1 V
CC
V
CC
+0.2 V
Analog input voltage (see Note 2) 0 V
CC
0 V
CC
V
High-level control input voltage, V
IH
2 2 V
Low-level control input voltage, V
IL
0.8 0.8 V
Setup time, address bits at data input before I/O CLOCK↑,
t
su(A)
200 400 ns
Hold time, address bits after I/O CLOCK↑,t
h(A)
0 0 ns
Setup time, CS low before clocking in first address bit, t
su(CS)
(see Note 3)
3 3
System
clock
cycles
CS high during conversion, t
wH(CS)
36 36
System
clock
cycles
I/O CLOCK frequency, f
clock(I/O)
0 2.048 0 1.1 MHz
Pulse duration, SYSTEM CLOCK frequency, f
clock(SYS)
f
clock(I/O)
4 f
clock(I/O)
2.1 MHz
Pulse duration, SYSTEM CLOCK high, t
wH(SYS)
110 210 MHz
Pulse duration, SYSTEM CLOCK low, t
wL(SYS)
100 190 MHz
Pulse duration, I/O clock high, t
wH(I/O)
200 404 ns
Pulse duration, I/O clock low, t
wL(I/O)
200 404 ns
System
f
clock(SYS)
≤ 1048 kHz 30 30
Clock transition time
System
f
clock(SYS)
> 1048 kHz 20 20
ns
(see Note 4)
I/O
f
clock(I/O)
≤ 525 kHz 100 100
ns
I/O
f
clock(I/O)
> 525 kHz 40 40
Operating free-air temperature, T
A
TLC540I, TLC541I –40 85 –40 85 °C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all 1s (11111111), while input voltages less than that applied to
REF– convert as all 0s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the
total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at CS
, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until
the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from V
IH
min to V
IL
max or to rise from V
IL
max to V
IH
min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.