Datasheet

   
      
    ± 
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
25
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operation cycle timing
4 SCLKs
4-bit Command 12-bit CFR Data (Optional)
12 SCLKs for Short
44 SCLKs for Long
4 SCLKs
12 SCLKs for Short
44 SCLKs for Long
Delay From
SDI
2-bit Don’t Care14-bit Data (Previous Conversion)
SDO
SDI
SDO
15 ns
15 nS
Active FS
t
(setup)
†
t
(sample)
t
(convert)
t
(overhead)
t
(delay)
†
t
(setup)
†
t
(sample)
t
(convert)
t
(overhead)
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CSTAR
(For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CS
Initiates
Operation
FS Initiates
Operation
18 OSC for Internal OSC
‡
72 SCLK for External Clock
18 OSC for Internal OSC
‡
72 SCLK for External Clock
4-bit Command 12-bit CFR Data (Optional)
2-bit Don’t Care
Active CS
(FS Is Tied to High)
Active CS
(CS Can Be Tied to Low)
14-bit Data (Previous Conversion)
§
§
CS
Low to FS High
†
Non JEDEC terms used.
‡
18 internal OSC or 72 SCLK for TLC3574 and TLC3578,
13 internal OSC or 52 SCLK for TLC2574 and TLC2578.
§
For TLC3574 and TLC3578, 14-bits are result of previous conversion, last two bits are don’t care. For TLC2574 and TLC2578, 12-bits are result
of previous conversion, last four bits are don’t care.