Datasheet

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      
    ± 
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
14
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timing requirements over recommended operating free-air temperature range, AV
DD
= 5 V,
DV
DD
= 5 V, V
REFP
= 4 V, V
REFM
= 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CS trigger
PARAMETERS MIN TYP MAX UNIT
t
su
(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load 12 ns
t
d(4)
Delay time, delay time from the falling edge of 16th SCLK to CS rising edge, at 25 pF load
(see Note 12)
5 ns
t
w(2)
Pulse width of CS high, at 25-pF load 1 t
c(1)
t
d(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
DV
DD
= 5 V 0 12
ns
t
d(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
final level), at 10 pF load
DV
DD
= 2.7 V
0 30
†
ns
t
d(6)
Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load 0 6 ns
t
d(7)
Delay time, delay from CS falling edge to INT rising edge, at 10-pF load
DV
DD
= 5 V 0 6
ns
t
d(7)
Delay time, delay from CS falling edge to INT rising edge, at 10-pF load
DV
DD
= 2.7 V 0 16
†
ns
†
Specified by design
NOTE 12: For normal short sampling, t
d(4)
is the delay time from the falling edge of 16th SCLK to CS
rising edge.
For normal long sampling, t
d(4)
is the delay time from the falling edge of 48th SCLK to CS
rising edge.
Hi-Z
ID15
OD1 OD0
ID1
116
OD15
Don’t Care ID0
OR
t
su(2)
t
d(4)
t
w(2)
t
d(7)
t
d(5)
Hi-Z Hi-Z
Don’t Care
V
IH
V
IL
CS
SCLK
SDI
SDO
EOC
INT
t
d(6)
Don’t Care
OD7OD15
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS
initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 2. Critical Timing for CS Trigger