Datasheet

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
interface with host
Figure 34 shows examples of the interface between a single converter and a host DSP (TMS320C54x DSP)
or microprocessor. The C54x is set as FWID = 1 (active pulse width = 1CLK), (R/X) DATDLY = 1 (1 bit data delay),
CLK(X/R)P = 0 (transmit data are clocked out at rising edge of CLK, receive data are sampled on falling edge
of CLK), and FS(X/R)P = 1 (FS is active high). If multiple converters connect to the same C54x, use CS
as the
chip select.
The host microprocessor is set as the SPI master with CPOL = 0 (active high clock), and CPHA = 1 (transmit
data is clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) per
transfer is required.
FSR
FSX
DX
DR
CLKR
CLKX
IRQ
TMS320C54X
Converter
10 kΩ
V
DD
CS
FS
SDI
SDO
SCLK
INT
/EOC
Ain
Single Converter Connects to DSP
SS
MOSI
MISO
SCK
IRQ
Host
Microprocessor
Converter
10 kΩ
V
DD
CS
FS
SDI
SDO
SCLK
INT
/EOC
Ain
Converter Connects to Microprocessor
10 kΩ
Figure 34. Typical Interface to Host DSP and Microprocessor
sampling time analysis
Figure 35 shows the equivalent analog input circuit of the converter. During the sampling, the input capacitor,
C
i
, has to be charged to V
C
, (V
C
= V
s
± voltage of 1/4 LSB = V
s
± [V
s
/65532] for 14 bit converter).
t
(s)
= R
t
× C
i
× In (65532) where R
t
= R
s
+r
i
, t
(s)
= Sampling time
V
I
= Input Voltage at AIN
V
S
= External Driving Source Voltage
R
S
= Source Resistance
r
i
= Equivalent Resistor of Mux., 1.5 kΩ
C
I
= Input Capacitance, 30 pF Max.
V
C
= Capacitance Charging Voltage
r
i
Data ConverterDriving Source
V
I
V
C
R
S
V
S
C
I
Figure 35. Equivalent Input Circuit Including the Driving Source
TMS320C54x is a trademark of Texas Instruments.