Datasheet

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operation cycle timing
4 SCLKs
4-bit Command 12-bit CFR Data (Optional)
12 SCLKs for Short
44 SCLKs for Long
4 SCLKs
12 SCLKs for Short
44 SCLKs for Longt–CSL to FSL
SDI
2-bit Don’t Care14-bit Data (Previous Conversion)
SDO
SDI
SDO
15 ns
15 nS
Active FS
t
(setup)
†
t
(sample)
t
(convert)
t
(overhead)
t
(delay)
†
t
(setup)
†
t
(sample)
t
(convert)
t
(overhead)
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CSTAR
(For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CS
Initiates
Operation
FS Initiates
Operation
18 OSC for Internal OSC
†
72 SCLK for External Clock
18 OSC for Internal OSC
72 SCLK for External Clock
4-bit Command 12-bit CFR Data (Optional)
2-bit Don’t Care
Active CS
(FS Is Tied to High)
Active CS
(CS Can Be Tied to Low)
†
Non JEDEC terms used.
14-bit Data (Previous Conversion)
After the operation is finished, the host has several choices. Table 3 summarizes operation options.