Datasheet

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
90%
10%
ID15
OD1
OD0
ID1
Hi-Z
50%
1
16
OD15
Don’t Care ID0
OR
V
IH
V
IL
t
w(1)
t
c(1)
t
su(1)
t
h(1)
t
h(2)
t
d(1)
t
d(2)
t
r(1)
t
f(1)
t
d(3)
Hi-Z
Don’t Care
t
f(1)
t
r(1)
CS
SCLK
SDI
SDO
EOC
INT
See Note A
See Note B
NOTES: A. For normal long sampling, t
d(2)
is the delay time of EOC low after the falling edge of 48th SCLK.
B. For normal long sampling, t
d(3)
is the delay time of INT
low after the falling edge of 48th SCLK.
– – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS
initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z; all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT