Datasheet

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AV
DD
= 5 V, DV
DD
= 5 V, V
REFP
= 5 V, V
REFM
= 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
PARAMETERS MIN TYP MAX UNIT
t
(1)
Cycle time of SCLK at 25
p
F load
DV
DD
= 2.7 V 100
ns
t
c(1)
Cycle time of SCLK at 25-pF load
DV
DD
= 5 V
40
†
ns
t
w(1)
Pulse width, SCLK high time at 25-pF load 40% 60% t
c(1)
t
Rise time for INT EOC at 10 pF load
DV
DD
= 5 V 6
ns
t
r(1)
Rise time for INT, EOC at 10-pF load
DV
DD
= 2.7 V
10
ns
t
Fall time for INT EOC at 10 pF load
DV
DD
= 5 V 6
ns
t
f(1)
Fall time for INT, EOC at 10-pF load
DV
DD
= 2.7 V
10
ns
t
su(1)
Setup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pF
load
6 – ns
t
h(1)
Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at
25-pF load
0 – ns
t
Dela
y
time
,
new SDO valid
(
reaches 90% of final level
)
after SCLK risin
g
DV
DD
= 5 V 0 10
ns
t
d(1)
Delay
time
,
new
SDO
valid
(reaches
90%
of
final
level)
after
SCLK
rising
edge, at 10-pF load
DV
DD
= 2.7 V
0 23
‡
ns
t
h(2)
Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF
load
0 – ns
td(2)
Delay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling,
at 10-pF load
0 6 ns
t
d(3)
Delay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pF
load [see the (‡) double dagger note and Note 6]
t
(conv)
t
(conv)
+ 6 µs
†
The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns.
‡
Specified by design
NOTE 6: For normal short sampling, t
d(3)
is the delay from 16th falling edge of SCLK to INT
falling edge.
For normal long sampling, t
d(3)
is the delay from 48th falling edge of SCLK to the falling edge of INT
.
Conversion time, t
(conv)
is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × t
c(1)
+ 15 ns when external
SCLK is conversion clock source.