Datasheet
SLAS345 − DECEMBER 2001
6
www.ti.com
timing requirements, V
DD
= 5 V, V
REF
= 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)
MIN TYP MAX UNIT
t
cyc(SCLK)
SCLK cycle time, V
DD
= 4.5 V to 5.5 V (see Note 3) 66 10000 ns
t
w1
Pulse duration, SCLK low 27 5000 ns
t
w2
Pulse duration, SCLK high 27 5000 ns
t
h1
Hold time, CS high after SCLK falling edge 3 ns
t
su1
Setup time, CS falling edge before the first SCLK falling edge 15 ns
t
h2
Hold time, CS low after 16th SCLK falling edge 5 ns
t
w3
Pulse duration, CS high 0.5 SCLKs
t
d1
Delay time, CS falling edge to SDO MSB valid, V
DD
= V
REF
= 4.5 V, 20 pF 12 17 ns
t
d2
Delay time, SCLK rising edge to next SDO data bit valid, V
DD
= V
REF
= 4.5 V, 20 pF 15 ns
t
d3
Delay time, 17
th
SCLK rising edge to 3-stated SDO, V
DD
= V
REF
= 4.5 V, 20 pF (see Note 4) 20 ns
t
su3
Setup time, CS falling edge before FS rising edge (TLC3541 only) 0.5 1 SCLKs
t
w4
Pulse duration, FS high (TLC3541 only) 0.5 1 SCLKs
t
su4
Setup time, FS rising edge before SCLK falling edge (TLC3541 only) 12.5 ns
t
h4
Hold time, FS high after SCLK falling edge (TLC3541 only) 5 ns
t
su5
Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only) 12 ns
t
d4
Delay time, FS rising edge to SDO MSB valid, (V
DD
= V
REF
= 4.5 V, 20 pF TLC3541 only) 15 ns
t
h6
Hold time, CS low after 1st SCLK falling edge 5 ns
t
su6
Setup time, CS rising edge before 9th (or the last) SCLK falling edge 5 ns
t
h7
Hold time, FS low after 1st SCLK falling edge (TLC3541 only) 5 ns
t
su7
Setup time, FS rising edge before 9th (or the last) SCLK falling edge 5 ns
t
cyc(reset)
Active CS/FS cycle time, SCLK falling edges required to initialize ADC 1 8 SCLKs
t
conv
Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC) 1.67 2.67 µs
t
s
Sample time, 20 SCLKs, SCLK up to 15 MHz 1.33 200 µs
NOTES: 3. Timing specifications given for 40/60 to 60/40 duty cycle
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS
edge if a 17th SCLK is not
presented.