Datasheet

 
SLAS345 − DECEMBER 2001
15
www.ti.com
PRINCIPLES OF OPERATION
1
1
MSB
98
2
2
MSB MSB MSB−1
198
2
OR
t
h7
t
su7
t
h7
t
su6
t
cyc(reset)
t
cyc(reset)
Normal Cycle Begin
s
Initialization Cycle (Reset)
SCLK
CS
FS
SDO
Figure 21. Critical Timing: Initialization Cycle (TLC3541 Only)
detailed description
The TLC3541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22
shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN (or the AIN(+) pin for
TLC3545) during the sampling period. When the conversion process starts, the SAR control logic and charge
redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the
comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the
ADC output code is generated.
AIN/
AIN(+)
+
−
GND/
AIN(−)
Charge
Redistribution
DAC
ADC Code
Control
Logic
C
i
C
i
Figure 22. Simplified SAR Circuit