Datasheet

5–1
5 Application Information
5.1 Single-Ended to Differential External Analog Front-End Circuit
(f
s
= 44.1 kHz)
A single-ended to differential external analog front-end example circuit is shown in Figure 5–1. It biases the
input signal around AV
DD
/2 and applies the maximum input signal of 0.7 Vrms. The device sees a full-scale
differential input voltage of approximately 4 V
pp
. For other maximum input signals, the ratio of R2/R1 can
be scaled accordingly to ensure a max ADC input of approximately 4 V
pp
. As required by the ADC, R5, C4,
and R6 provide a single-pole low-pass antialiasing filter to attenuate unwanted frequencies. If the user
chooses to supply a single-ended input directly to the device (2 V
pp
max), performance will be significantly
degraded.
_
+
10 kΩ
47 µF
AV
DD
/2
10 kΩ
10 pF
_
+
10 kΩ
10 pF
499 Ω
1000 pF
AINRM
AINRP
10 kΩ
5 V
GND
R1
C1
8
2
3
4
1
U3:A
R2
R3
C2
R4
C3
R5
C4
499 Ω
R6
Antialiasing
Filter
Right Channel
Analog Input
0.7 V
rms
4 V
PP
6
5
7
U3:B
211
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Figure 5–1. Analog Front End (right channel) for 0.7 Vrms Input