Datasheet

4–1
4 Parameter Measurement Information
t
wH(MCLK)
t
wL(MCLK)
MCLK
Figure 4–1. Master Clock Timing
t
d(SDOUT)
t
d(LRCLK)
t
su(SDIN)
t
h(SDIN)
SCLK
LRCK
SDOUT
SDIN
Figure 4–2. Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing
SCLK
t
d(SDOUT)
t
h(SDIN)
t
su(SDIN)
SDOUT
SDIN
LRCLK
t
d(FS)
t
w(FSHIGH)
Figure 4–3. DSP Serial Port Timing