Datasheet

3–4
3.4 Serial Interface Switching Characteristics, T
A
= 25°C,
AV
DD
= DV
DD
= 3.3 V ± 10%
PARAMETER MIN TYP MAX UNIT
f
(SCLK)
SCLK frequency 6.144 MHz
t
d(LRCLK)
Delay time, LRCLK edge to SCLK rising 20 1/(128×f
s
) ns
t
d(SDOUT)
Delay time, SDOUT valid from SCLK falling
(see Note 10)
(1/(256×f
s
))+10 ns
t
su(SDIN)
SDIN setup time before SCLK rising edge 20 ns
t
h(SDIN)
SDIN hold time from SCLK rising edge 10 ns
f
(LRCLK)
LRCLK frequency 16 44.1 96 kHz
MCLK duty cycle 50%
SCLK duty cycle 50%
LRCLK duty cycle 50%
NOTE 10: Maximum of 50-pF external load on SDOUT
3.5 DSP Serial Interface Switching Characteristics, T
A
= 25°C,
AV
DD
= DV
DD
= 3.3 V ± 10% (see Note 11)
PARAMETER MIN TYP MAX UNIT
f
(SCLK)
SCLK frequency 6.144 MHz
t
d(FS)
Delay time, SCLK rising to Fs 25 ns
t
w(FSHIGH)
Pulse duration, sync 1/(64×f
s
) ns
t
d(SDOUT)
Delay time, SDOUT valid from SCLK rising
(see Note 12)
(1/(256×f
s
))+10 ns
t
su(SDIN)
SDIN and LRCLK setup time before SCLK falling
edge
20 ns
t
h(SDIN)
SDIN and LRCLK hold time from SCLK falling edge 10 ns
SCLK duty cycle 50%
NOTES: 11. Burst mode is not supported.
12. Timing parameters for DSP format which samples on the falling edge