Datasheet

2–3

MODE MOD2 PIN MOD1 PIN MOD0 PIN SERIAL INTERFACE SDIN (DAC)/SDOUT (ADC)

0 0 0 0 16-bit, MSB first, right justified/left justified

1 0 0 1 20-bit, MSB first, right justified/left justified

2 0 1 0 24-bit, MSB first, right justified/left justified

3 0 1 1 16-bit IIS

4 1 0 0 20-bit IIS

5 1 0 1 24-bit IIS

6 1 1 0 16-bit MSB first, left justified/left justified

7 1 1 1 16-bit DSP frame (see Note 1)

NOTE 1: For the 16-bit DSP frame use SCLK = 64 f

2.14.1 MSB First Right/Left Justified Format

Left Channel Right Channel

MSBX LSB MSBX

LSB MSB LSB

SDOUT

SDIN

LRCLK = f

SCLK

MSB

LSB

Figure 2–1. MSB First Right/Left Justified (for 16-, 20-, and 24-bits)

Note the following characteristics of this protocol.

• Left channel data is valid when LRCLK is high.

• The SDIN (recorded data) data is justified to the trailing edge of LRCLK

• The SDOUT MSB (playback data) is transmitted at the same time as the LRCLK edge, and

captured at the very next rising edge of SCLK.

• If LRCLK phase changes by more than 10 MCLKs, then the device is automatically reset.