TLC320AD77C 24ĆBit 96 kHz Stereo Audio Codec Data Manual 1999 Mixed Signal Linear Products
Printed in U.S.A.
TLC320AD77C 24-Bit 96 kHz Stereo Audio Codec Data Manual SLAS194 August1999 Printed on Recycled Paper
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Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 3.5 3.3.2 ADC Digital Filter, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Analog-to-Digital Converter, TA = 25°C, AVDD = DVDD = 3.3 V, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . 3.3.4 DAC Interpolation Filter, TA = 25°C, AVDD = DVDD = 3.3 V + 10%, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.
1 Introduction The TLC320AD77C is a cost competitive stereo analog-to-digital (A/D) and digital-to-analog (D/A) 24-bit delta-sigma converter for consumer applications which demand excellent audio performance. It has a wide variety of serial input options including left justified, right justified, IIS, or DSP data formats for 16-, 20-, or 24-bit input/output data. It has an extremely wide range of sampling rates starting at 16 kHz and increasing upwards to 96 kHz.
1.
1.3 Terminal Assignments DB PACKAGE (TOP VIEW) 1.
1.5 Terminal Functions TERMINAL NAME AINLM NO.
2 Functional Description 2.1 ADC Channel To produce excellent common-mode rejection of unwanted signals, the analog signal is processed differentially until it is converted to digital data. A single-ended input signal must be converted into a differential input and filtered with a single-pole antialiasing filter before entering the ADC input. (See Section 2.7, ADC Analog Input).
2.7 ADC Analog Input The ADC accepts a differential input with a maximum value that does not exceed approximately 4 Vpp. See Section 5.1, Single-Ended to Differential External Analog Front-End Circuit for a description of the recommended external analog front end. 2.8 DAC Analog Output The DAC outputs a single-ended signal with a max value of 0.7 Vrms. See Section 5.2, External Analog Back-End Circuit for a description of the recommended back-end circuit. 2.
MODE MOD2 PIN MOD1 PIN MOD0 PIN 0 0 0 0 16-bit, MSB first, right justified/left justified SERIAL INTERFACE SDIN (DAC)/SDOUT (ADC) 1 0 0 1 20-bit, MSB first, right justified/left justified 2 0 1 0 24-bit, MSB first, right justified/left justified 3 0 1 1 16-bit IIS 4 1 0 0 20-bit IIS 5 1 0 1 24-bit IIS 6 1 1 0 16-bit MSB first, left justified/left justified 7 1 1 1 16-bit DSP frame (see Note 1) NOTE 1: For the 16-bit DSP frame use SCLK = 64 fs. 2.14.
2.14.2 IIS-Compatible Serial Format SCLK LRCLK = fs SDIN X MSB LSB X MSB LSB SDOUT X MSB LSB X MSB LSB Left Channel Right Channel Figure 2–2. IIS-Compatible Serial Format (for 16-, 20-, and 24-bits) Note the following characteristics of this protocol. • Left channel data is valid when LRCLK is low. • SDIN is sampled with the rising edge of SCLK. • SDOUT is transmitted on the falling edge of SCLK.
2.14.4 DSP Compatible Serial Interface Format SCLK LRCLK = fs SDIN 15 14 13 0 15 14 13 0 SDOUT 15 14 13 0 15 14 13 0 Left Channel (MSB = 15) Right Channel (MSB = 15) Figure 2–4. DSP Compatible Serial Interface Format (for 16-bits) Note the following characteristics of this protocol. • MCLK = 256 Fs only • SCLK = 64 times the sampling frequency. • Serial data is sampled with the falling edge of SCLK. • Serial data is transmitted on the rising edge of SCLK. 2.
2.16.2 Power Down/Reset The TLC320AD77C is capable of entering a stand-by mode at reduced power when no activity is required. To initiate the reset sequence, PDN_RSTB is held low for a minimum of 10 ns. As long as the pin is held low, the device is in the power-down state. In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the PDN_RSTB pin goes low. Otherwise, the device may drain additional supply current. 2.16.
3 Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)† Analog supply voltage range, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.2 V Digital supply voltage range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.2 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . .
3.3.2 ADC Digital Filter, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz (see Notes 3 and 4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Decimation Filter (LPF) Pass band 20 Pass band ripple Stop band Stop band attenuation kHz ±0.01 dB 24.1 kHz 80 Group delay dB µs 720 ADC High-Pass Filter (HPF) Pass band (–3 dB) Deviation from linear phase 20 Hz to 20 kHz 0.87 Hz 1.23 degree NOTES: 3. All the terms characterized by frequency, scale with the chosen sampling frequency, fs. 4.
3.3.5 Digital-to-Analog Converter, TA = 25°C, AVDD = 3.3 V, fs = 44.1 kHz, Input = 1 Vrms Sine Wave at 1 kHz (see Note 3) PARAMETER SNR TEST CONDITIONS MIN TYP MAX A-weighted 100 dB Dynamic range A-weighted, –60 dB, f = 1 kHz 100 dB Signal-to-noise + distortion ratio 0 dB, 1 kHz 80 dB Power supply rejection ratio 1 kHz 50 dB 120 dB Idle tone rejection Intermodulation distortion –75 Frequency response –0.5 dB 0.5 Deviation from linear phase ±1.
3.4 Serial Interface Switching Characteristics, TA = 25°C, AVDD = DVDD = 3.3 V ± 10% PARAMETER f(SCLK) td(LRCLK) td(SDOUT) MIN TYP SCLK frequency Delay time, LRCLK edge to SCLK rising tsu(SDIN) th(SDIN) SDIN setup time before SCLK rising edge 20 SDIN hold time from SCLK rising edge 10 f(LRCLK) LRCLK frequency 16 UNIT 6.144 MHz 1/(128×fs) ns (1/(256×fs))+10 ns 20 Delay time, SDOUT valid from SCLK falling (see Note 10) MAX ns ns 44.
4 Parameter Measurement Information MCLK twH(MCLK) twL(MCLK) Figure 4–1. Master Clock Timing SCLK td(LRCLK) LRCK ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td(SDOUT) SDOUT tsu(SDIN) th(SDIN) SDIN Figure 4–2. Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing SCLK td(FS) tw(FSHIGH) LRCLK ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ td(SDOUT) SDOUT tsu(SDIN) th(SDIN) SDIN Figure 4–3.
0 R Amplitude – dB –20 –40 –60 –80 –100 0 fs/2 3 fs 2 fs f – Frequency – Hz 1 fs 4 fs 5 fs Figure 4–4. DAC Filter Overall Frequency Characteristics Amplitude – dB 0.1 0.05 0 –0.05 –0.1 0 0.1 fs 0.2 fs 0.3 fs f – Frequency – Hz 0.4 fs 0.5 fs Figure 4–5. DAC Digital Filter Passband Ripple Characteristics 50 Amplitude – dB 0 –50 –100 –150 –200 0 2 fs 4 fs 6 fs f – Frequency – Hz 8 fs 10 fs Figure 4–6.
0 Amplitude – dB –20 –40 –60 –80 –100 0 0.2 fs 0.4 fs 0.6 fs f – Frequency – Hz 0.8 fs 1 fs Figure 4–7. ADC Digital Filter Stopband Characteristics 0.008 Amplitude – dB 0.006 0.004 0.002 0 –0.002 0 0.1 fs 0.2 fs 0.3 fs f – Frequency – Hz 0.4 fs 0.5 fs Figure 4–8. ADC Digital Filter Passband Characteristics 0.2 Amplitude – dB 0 –0.2 –0.4 –0.6 –0.8 –1 0 1 fs 2 fs f – Frequency – Hz 3 fs 4 fs Figure 4–9.
4–4
5 Application Information 5.1 Single-Ended to Differential External Analog Front-End Circuit (fs = 44.1 kHz) A single-ended to differential external analog front-end example circuit is shown in Figure 5–1. It biases the input signal around AVDD/2 and applies the maximum input signal of 0.7 Vrms. The device sees a full-scale differential input voltage of approximately 4 Vpp. For other maximum input signals, the ratio of R2/R1 can be scaled accordingly to ensure a max ADC input of approximately 4 Vpp.
5.2 External Analog Back-End Circuit (fs = 44.1 kHz) For specified performance, the output should be taken between VCOM and AOUTR (or AOUTL). At pins AOUTR and AOUTL the output is an inverted analog representation of the digital input signal. It is advisable to add a low-pass filter to the output of the TLC320AD77C to eliminate high frequency noise >80 kHz. See Figure 5–2 for the recommended analog back-end circuit. The output of this circuit provides the user with a noninverted signal.
Vref Filter VREFM 1 1 C7 1 µF 2 VREFP 2 C8 0.1 µF 1 2 1 FB1 AVSS(REF) 2 U2 7 23 11 17 14 15 16 18 19 8 9 10 21 20 22 28 27 1 2 12 AVSS AVDD DVSS DVDD C9 0.1 µF 2 VREFM VREFP AVSS(REF) VRFILT 4 3 6 5 1 1 C10 15 µF 2 C11 0.1 µF VRFILT SCLK MCLK LRCLK DEM0 DEM1 MOD2 MOD1 MOD0 SPDMODE PDN_RSTB TEST AINRM AINRP AINLM AINLP SDIN SDOUT AOUTR VCOM AOUTL 13 26 25 24 TLC320AD77 Figure 5–3.
5–4
Appendix A Mechanical Data DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 5,60 5,00 8,20 7,40 Gage Plane 1 14 0,25 A 0°– 8° 1,03 0,63 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 A MAX 3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 2,70 5,90 5,90 6,90 7,90 9,90 DIM 28 30 38 9,90 12,30 4040065 / C 10/95 NOTES: A. B. C. D. All linear dimensions are in millimeters.
A–2
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC320AD77CDBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.1 10.4 2.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC320AD77CDBR SSOP DB 28 2000 346.0 346.0 33.