Datasheet

  
 
 
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
full-power response (continued)
(a) f = 100 Hz (b) B
OM
> f > 100 Hz (c) f = B
OM
(d) f > B
OM
Figure 37. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
While the TLC27L1 performs well using dual
power supplies (also called balanced or split
supplies), the design is optimized for
single-supply operation. This includes an input
common-mode voltage range that encompasses
ground as well as an output voltage range that
pulls down to ground. The supply voltage range
extends down to 3 V (C-suffix types), thus allowing
operation with supply levels commonly available
for TTL and HCMOS; however, for maximum
dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference
level (see Figure 38). The low-input bias-current consumption of the TLC27L1 permits the use of very large
resistive values to implement the voltage divider, thus minimizing power consumption.
The TLC27L1 works well in conjunction with digital logic; however, when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device
supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.
−
+
R4
V
O
V
DD
R2
R1
V
I
V
ref
R3
C
0.01 µF
V
ref
+ V
DD
R3
R1 ) R3
V
O
+ (V
ref
* V
I
)
R4
R2
) V
ref
Figure 38. Inverting Amplifier With Voltage
Reference