Datasheet
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload
recovery time. If desired, an output clamp pin is available to reduce the recovery time even further.
The device inputs and output are designed to withstand ±100-mA surge currents without sustaining latch-up.
Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from −40°C to125°C.
The M-suffix devices are characterized for operation over the full military temperature range of −55°C to125°C.
AVAILABLE OPTIONS
(1)
PACKAGED DEVICES
V
IO
max
8 PIN 14 PIN 20 PIN
CHIP
FORM
T
A
V
IO
max
AT 25°C
SMALL
OUTLINE
(D008)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
SMALL
OUTLINE
(D014)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
CHIP
CARRIER
(FK)
CHIP
FORM
(Y)
0
°
C
1 µV
TLC2652AC-8D
—
TLC2652ACP
TLC2652AC-14D
—
TLC2652ACN
—
0 C
to
70 C
1 µV
3 µV
TLC2652AC-8D
TLC2652C-8D
—
—
TLC2652ACP
TLC2652CP
TLC2652AC-14D
TLC2652C-14D
—
—
TLC2652ACN
TLC2652CN
—
—
TLC2652Y
to
70°C
3
µ
V
TLC2652C-8D
—
TLC2652CP
TLC2652C-14D
—
TLC2652CN
—
TLC2652Y
−40
°
C
1 µV
TLC2652AI-8D
—
TLC2652AIP
TLC2652AI-14D
—
TLC2652AIN
—
−40 C
to
85 C
1 µV
3 µV
TLC2652AI-8D
TLC2652A-8D
—
—
TLC2652AIP
TLC2652IP
TLC2652AI-14D
TLC2652I-14D
—
—
TLC2652AIN
TLC2652IN
—
—
—
to
85°C
3
µ
V
TLC2652A-8D
—
TLC2652IP
TLC2652I-14D
—
TLC2652IN
—
—
−40
°
C
−40 C
to
125 C
3.5 µV TLC2652Q-8D — — — — — — —
to
125°C
3.5 µV
TLC2652Q-8D
—
—
—
—
—
—
—
−55°C
to
3 µV
TLC2652AM-8D
TLC2652AMJG
TLC2652AMP
TLC2652AM-14D
TLC2652AMJ
TLC2652AMN
TLC2652AMFK
—
to
125°C
3 µV
3.5 µV
TLC2652AM-8D
TLC2652M-8D
TLC2652AMJG
TLC2652MJG
TLC2652AMP
TLC2652MP
TLC2652AM-14D
TLC2652M-14D
TLC2652AMJ
TLC2652MJ
TLC2652AMN
TLC2652MN
TLC2652AMFK
TLC2652MFK
—
The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C.
NOTE (1): For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
functional block diagram
Clamp
Circuit
CLAMP
OUT
C RETURN
V
DD−
Compensation-
Biasing
Circuit
V
DD+
A
B
B
A
IN+
IN−
C
XA
C
XB
External
Components
Null
Main
+
−
+
−
AB
DISTRIBUTION OF TLC2652
INPUT OFFSET VOLTAGE
Percentage of Units − %
V
IO
− Input Offset Voltage − µV
−3 −2 −1 0 1 2
3
0
4
8
12
16
20
24
28
32
36
150 Units Tested From 1 Wafer Lot
V
DD±
= ±5 V
T
A
= 25°C
N Package
C
IC
5
4
2
3
6
7
8
Pin numbers shown are for the D (14 pin), JG, and N packages.