Datasheet

   
      
    ± 
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
31
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conversion operation (continued)
CS
FS
SDI
INT
SDO
*** Command = Configure Write for Mode 11, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0−0−2−2
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
*
Configure
Conversion
From CH0
Conversion
From CH2
Conversion
From CH2
Conversion
From CH0
1st SWEEP
1st FIFO Read
REPEAT
2nd FIFO Read
CH0 CH0 CH2 CH2 CH0
READ FIFO after 1st SWEEP Completed
CSTART
*** ** ****** *
Possible Signal
Don’t Care
Figure 19. Mode 11, CSTART Triggers Samplings/Conversions, FS Initiates SELECT Operation
conversion clock and conversion speed
The conversion clock source can be the internal OSC, or the external clock, SCLK. The conversion clock is equal
to the internal OSC if the internal clock is used, or equal to SCLK/4 when the external clock is selected. It takes
18 conversion clocks plus 15 ns to finish the conversion for TLC3574 and TLC3578, and 13 conversion clocks
plus 15 ns for the TLC2574 and TLC2578. If the external clock is selected, the conversion time (not including
sampling time) is 18X(4/f
SCLK
)+15 ns for TLC3574 and TLC3578 and 13X(4/f
SCLK
)+15 ns for TLC2574 and
TLC2578. Table 4 shows the maximum conversion rate (including sampling time) when the analog input source
resistor is 25 Ω.
Table 4. Maximum Conversion Rate
DEVICE SAMPLING MODE CONVERSION CLK
MAX SCLK
(MHz)
CONVERSION
TIME (µs)
RATE
(KSPS)
SHORT (16 SCLK) External SCLK/4 10 8.815 113.4
TLC3574/78
LONG (48 SCLK) External SCLK/4 25 4.815 207.7
TLC3574/78
(Rs = 25 Ω)
SHORT (16 SCLK) Internal 6.5 MHz 10 4.384 228.0
(Rs = 25 )
LONG (48 SCLK) Internal 6.5 MHz 25 4.705 212.5
SHORT (16 SCLK) Exernal SCLK/4 10 6.815 146.7
TLC2574/78
LONG (48 SCLK) External SCLK/4 25 4.015 249.1
TLC2574/78
(Rs = 25 Ω)
SHORT (16 SCLK) Internal 6.5 MHz 10 3.615 276.6
(Rs = 25 )
LONG (48 SCLK) Internal 6.5 MHz 25 3.935 254.1