Datasheet

TAS5414A, TAS5424A
SLOS535C –MAY 2009– REVISED APRIL 2011 www.ti.com
Table 1. TERMINAL FUNCTIONS
TERMINAL
PHD
DKD Package
Package TYPE
(1)
DESCRIPTION
NAME
TAS5414A TAS5424A TAS5414A
NO. NO. NO.
A_BYP 13 14 11 PBY Bypass pin for the AVDD analog regulator
CLIP_OT Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It
9 10 6 DO
W also reports tweeter detection during tweeter mode.
CP 28 34 41 CP Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT 27 33 40 CP Bottom of flying capacitor for charge pump
CPC_TOP 29 35 42 CP Top of flying capacitor for charge pump
D_BYP 8 9 5 PBY Bypass pin for DVDD regulator output
FAULT 5 5 1 DO Global fault output (open drain): UV, OV, OTSD, OCSD, DC
3, 7, 8, 9, 12,
14, 16, 17,
21, 22, 23,
24, 25, 26,
7, 11, 12,
10, 11, 23, 30, 31, 32, AG / DG /
GND 28, 29, 32, Ground
26, 32 35, 38, 39, PGND
38, 39
43, 46, 49,
50, 51, 55,
56, 57, 58,
59, 60
I2C_ADDR 2 2 62 AI I
2
C address bit
IN1_M N/A 16 N/A AI Inverting analog input for channel 1 (TAS5424A only)
IN1_P 14 15 13 AI Non-inverting analog input for channel 1
IN2_M N/A 18 N/A AI Inverting analog input for channel 2 (TAS5424A only)
IN2_P 15 17 15 AI Non-inverting analog input for channel 2
IN3_M N/A 20 N/A AI Inverting analog input for channel 3 (TAS5424A only)
IN3_P 17 19 19 AI Non-inverting analog input for channel 3
IN4_M N/A 22 N/A AI Inverting analog input for channel 4 (TAS5424A only)
IN4_P 18 21 20 AI Non-inverting analog input for channel 4
IN_M 16 N/A 18 ARTN Signal return for the 4 analog channel inputs (TAS5414A only)
MUTE 6 6 2 AI Gain ramp control: mute (low), play (high)
OSC_SYN Oscillator sync input from master or output to slave amplifiers (20 MHz
1 1 61 DI/DO
C divided by 5, 6, or 7)
OUT1_M 34 41 48 PO – polarity output for bridge 1
OUT1_P 33 40 47 PO + polarity output for bridge 1
OUT2_M 31 37 45 PO – polarity output for bridge 2
OUT2_P 30 36 44 PO + polarity output for bridge 2
OUT3_M 25 31 37 PO – polarity output for bridge 3
OUT3_P 24 30 36 PO + polarity output for bridge 3
OUT4_M 22 27 34 PO – polarity output for bridge 4
OUT4_P 21 26 33 PO + polarity output for bridge 4
19, 20, 35, 23, 24, 25, 27, 28, 29,
PVDD PWR PVDD supply
36 42, 43, 44 52, 53, 54
REXT 12 13 10 AI Precision resistor pin to set analog reference
SCL 4 4 64 DI I
2
C clock input from system I
2
C master
SDA 3 3 63 DI/DO I
2
C data I/O for communication with system I
2
C master
STANDBY 7 8 4 DI Active-low STANDBY pin. Standby (low), power up (high)
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,
PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.
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