Datasheet

LoadDump
Protection
29V–50V
OVProtectionRegion23V–29V
OV
Deglitch Time
Oscillator
Start-Up Time
t
0
t
1
t
2
t
3
Outputs
Pulled
Down
Time
26V
23V
50V
OV
Reset
LD
Reset
PVDD
FAULT
I C
CLK
2
15-VOUTx_P or
OUTx_M(Filtered)
ReadytoGet
OutofHi-Z
State
FaultDoesNotResetUntilFault
Register1IsRead
T0191-01
TAS5414A, TAS5424A
www.ti.com SLOS535C –MAY 2009– REVISED APRIL 2011
Figure 22. Sequence of Events for Supply Transition Back Into Normal Operating Region
Power Shutdown and Restart Sequence Control
The gain ramp of the filtered output signal and the updating of the I
2
C registers correspond to the MUTE pin
voltage during the ramping process. For the decreasing gain ramp (when transitioning from Play to Mute mode),
the actual decrease in output gain begins when the MUTE pin voltage is approximately 2/3 of the A_BYP
voltage, and the ramp itself completes when the MUTE pin voltage is approximately 1/3 of A_BYP. However, the
I
2
C register indicating that Mute mode has been entered does not update externally until the MUTE pin voltage is
approximately 1/10 of the A_BYP voltage. Conversely, for the increasing ramp process (when transitioning from
Mute to Play), the actual increase in output gain begins when the MUTE pin voltage is approximately 1/3 of the
A_BYP voltage and the gain increase completes when the MUTE pin voltage is approximately 2/3 of A_BYP. The
I
2
C register indicating Play mode has been entered updates when the MUTE pin voltage is approximately 9/10 of
the A_BYP voltage. For both gain ramps, the change in MUTE pin voltage begins when the I
2
C command to
change operating modes is received by the device. The length of time that the MUTE pin takes to complete its
ramp is dictated by the value of the external capacitor on the MUTE pin.
Copyright © 2009–2011, Texas Instruments Incorporated 31