Datasheet

SCL
SDA
t
w(H)
t
w(L)
t
r
t
f
t
su1
t
h1
T0027-01
SCL
SDA
t
h2
t
(buf)
t
su2
t
su3
Start
Condition
Stop
Condition
T0028-01
TAS5414A, TAS5424A
SLOS535C –MAY 2009– REVISED APRIL 2011 www.ti.com
TIMING REQUIREMENTS FOR I
2
C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
r
Rise time for both SDA and SCL signals 1000 ns
t
f
Fall time for both SDA and SCL signals 300 ns
t
w(H)
SCL pulse duration, high 4 μs
t
w(L)
SCL pulse duration, low 4.7 μs
t
su2
Setup time for START condition 4.7 μs
t
h2
START condition hold time after which first clock pulse is generated 4 μs
t
su1
Data setup time 250 ns
t
h1
Data hold time 0
(1)
ns
t
su3
Setup time for STOP condition 4 μs
C
B
Load capacitance for each bus line 400 pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
Figure 1. SCL and SDA Timing
Figure 2. Timing for Start and Stop Conditions
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