Datasheet

TAS5414A, TAS5424A
www.ti.com SLOS535C –MAY 2009– REVISED APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): T
Case
= 25°C, PVDD = 14.4 V, R
L
= 4 Ω, f
S
= 417 kHz, P
out
= 1 W/ch, Rext = 20 kΩ,
AES17 Filter, master mode operation (see application diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FAULT pin output voltage for logic-level high
V
OH_FAULT
2.4
(open-drain logic output)
External 47-kΩ pullup resistor to 3 V–5.5 V V
FAULT pin output voltage for logic-level low
V
OL_FAULT
0.5
(open-drain logic output)
OPEN/SHORT DIAGNOSTICS
Maximum resistance to detect a short from
R
S2P
, R
S2G
200 Ω
OUT pin(s) to PVDD or ground
Minimum load resistance to detect open
R
OPEN_LOAD
Including speaker wires 300 800 1300 Ω
circuit
Maximum load resistance to detect short
R
SHORTED_LOAD
Including speaker wires 0.5 1 1.5 Ω
circuit
I
2
C ADDRESS DECODER
t
LATCH_I2CADDR
300 μs
Time delay to latch I
2
C address after POR
Voltage on I2C_ADDR pin for address 0 Connect to GND 0% 0% 15%
Voltage on I2C_ADDR pin for address 1 25% 35% 45%
External resistors in series between D_BYP and GND as
V
I2C_ADDR
V
D_BYP
a voltage divider
Voltage on I2C_ADDR pin for address 2 55% 65% 75%
Voltage on I2C_ADDR pin for address 3 Connect to D_BYP 85% 100% 100%
I
2
C
Power-on hold time before I
2
C
t
HOLD_I2C
STANDBY high 1 ms
communication
f
SCL
SCL clock frequency 100 kHz
V
IH_SCL
SCL pin input voltage for logic-level high 2.1 5.5 V
R
PU_I2C
= 5-kΩ pullup, supply voltage = 3.3 V or 5 V
V
IL_SCL
SCL pin input voltage for logic-level low –0.5 1.1 V
I
2
C read, R
I2C
= 5-kΩ pullup,
V
OH_SDA
SDA pin output voltage for logic-level high 2.4 V
supply voltage = 3.3 V or 5 V
V
OL_SDA
SDA pin output voltage for logic-level low 0 0.4 V
I
2
C read, 3-mA sink current
I
2
C write, R
I2C
= 5-kΩ pullup,
V
IH_SDA
SDA pin input voltage for logic-level high 2.1 5.5 V
supply voltage = 3.3 V or 5 V
I
2
C write, R
I2C
= 5-kΩ pullup,
V
IL_SDA
SDA pin input voltage for logic-level low –0.5 1.1 V
supply voltage = 3.3 V or 5 V
C
I
Capacitance for SCL and SDA pins 10 pF
OSCILLATOR
OSC_SYNC pin output voltage for
V
OH_OSCSYNC
2.4 3.6 V
logic-level high
I2C_ADDR pin set to MASTER mode
OSC_SYNC pin output voltage for
V
OL_OSCSYNC
0.5 V
logic-level low
OSC_SYNC pin input voltage for logic-level
V
IH_OSCSYNC
2 3.6 V
high
I2C_ADDR pin set to SLAVE mode
OSC_SYNC pin input voltage for logic-level
V
IL_OSCSYNC
0.8 V
low
I2C_ADDR pin set to MASTER mode, f
S
= 500 kHz 3.76 4.0 4.24
f
OSC_SYNC
OSC_SYNC pin clock frequency I2C_ADDR pin set to MASTER mode, f
S
= 417 kHz 3.13 3.33 3.63 MHz
I2C_ADDR pin set to MASTER mode, f
S
= 357 kHz 2.68 2.85 3.0
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