Datasheet

TAS5414A, TAS5424A
SLOS535C –MAY 2009– REVISED APRIL 2011 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): T
Case
= 25°C, PVDD = 14.4 V, R
L
= 4 Ω, f
S
= 417 kHz, P
out
= 1 W/ch, Rext = 20 kΩ,
AES17 Filter, master mode operation (see application diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
A_BYP_UV_SET
A_BYP UV voltage 4.8 V
V
A_BYP_UV_CLEAR
Recovery voltage A_BYP UV 5.3 V
DVDD
V
D_BYP
D_BYP pin voltage 3.3 V
POWER-ON RESET (POR)
Maximum PVDD voltage for POR; I
2
C active
V
POR
6 V
above this voltage
V
POR_HY
PVDD recovery hysteresis voltage for POR 0.1 V
REXT
V
REXT
Rext pin voltage 1.24 V
CHARGE PUMP (CP)
V
CPUV_SET
CP undervoltage 4.8 V
V
CPUV_CLEAR
Recovery voltage for CP UV 5.2 V
OVERTEMPERATURE (OT) PROTECTION
T
OTW1_CLEAR
102 115 128
T
OTW1_SET
/
112 125 138
T
OTW2_CLEAR
Junction temperature for overtemperature
T
OTW2_SET
/
warning
122 135 148
T
OTW3_CLEAR
°C
T
OTW3_SET
/
132 145 158
T
OTSD_CLEAR
Junction temperature for overtemperature
T
OTSD
142 155 168
shutdown
CURRENT LIMITING PROTECTION
I
LIM1
Current limit 1 (load current) Load < 4 Ω 5.5 7.3 9 A
Current limit 2 (load current), through I
2
C
I
LIM2
Load < 2 Ω 8.5 11 13.5 A
setting
OVERCURRENT (OC) SHUTDOWN PROTECTION
I
MAX1
Maximum current 1 (peak output current) 9.5 11.3 13 A
Any short to supply, ground, or other channels
I
MAX2
Maximum current 2 (peak output current) 11.5 14.3 17 A
TWEETER DETECT
I
TH_TW
Load current threshold for tweeter detect 325 540 750 mA
I
LIM_TW
Load current limit for tweeter detect 2 A
STANDBY MODE
V
IH_STBY
STANDBY input voltage for logic-level high 2 5.5 V
V
IL_STBY
STANDBY input voltage for logic-level low 0 0.7 V
I
STBY_PIN
STANDBY pin current 0.1 0.2 μA
MUTE MODE
G
MUTE
Output attenuation MUTE pin ≤ 0.9 Vdc, V
IN
= 1 Vrms on all inputs 85 dB
DC DETECT
V
TH_DCD_POS
DC detect positive threshold default value PVDD = 14.4 Vdc, register 0x0E = 8EH 6.5 V
V
TH_DCD_NEG
DC detect negative threshold default value PVDD = 14.4 Vdc, register 0x0F = 3DH –6.5 V
DC detect step response time for four
t
DCD
4.3 s
channels
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
V
OH_CLIPOTW
2.4 V
high (open-drain logic output)
External 47-kΩ pullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic level
V
OL_CLIPOTW
0.5 V
low (open-drain logic output)
CLIP_OTW signal delay when output
t
DELAY_CLIPDET
20 μs
clipping detected
FAULT REPORT
10 Copyright © 2009–2011, Texas Instruments Incorporated