Datasheet

TLC226x, TLC226xA, TLC226xY
Advanced LinCMOS
 RAIL-TO-RAIL
OPERATIONAL AMPLIFIERS
SLOS177 – FEBRUARY 1997
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLC226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 52
and Figure 53 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (R
null
= 0).
A smaller series resistor (R
null
) at the output of the device (see Figure 56) improves the gain and phase margins
when driving large capacitive loads. Figure 52 and Figure 53 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
∆Θ
m1
tan
–1
2 × π × UGBW × R
null
× C
L
where :
(1)
∆Θ
m1
improvement inphasemargin
UGBW unity-gainbandwidthfrequency
R
null
output seriesresistance
C
L
loadcapacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 54). To
use equation 1, UGBW must be approximated from Figure 54.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 55. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F
1
1 g
m
× R
null
where :
(2)
F factor reducingfrequencyof pole
g
m
small-signaloutput transconductance (typically 4.83 × 10
–3
mhos)
R
null
output series resistance
For the TLC226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with C
L
: at C
L
= 10 pF, use 70 MHz, at C
L
= 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation in equation 1 to better approximate the
improvement in phase margin.