Datasheet

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C – DECEMBER 1992 – REVISED MARCH 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz
PARAMETER TEST CONDITIONS MIN MAX UNIT
E
L
Linearity error (see Note 6) ±1 LSB
E
ZS
Zero-scale error (see Note 7) See Note 2 ±1 LSB
E
FS
Full-scale error (see Note 7) See Note 2 ±1 LSB
Total unadjusted error (see Note 8) ±1 LSB
t
conv
Conversion time See Figures 6–10 21 µs
t
c
Total cycle time (access, sample, and conversion)
See Figures 6–10,
See Note 9
21
+10 I/O
CLOCK
periods
µs
t
v
Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 5 10 ns
t
d(I/O-DATA)
Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 5 240 ns
t
PZH
, t
PZL
Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
t
PHZ
, t
PLZ
Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 180 ns
t
r(bus)
Rise time, data bus See Figure 5 300 ns
t
f(bus)
Fall time, data bus See Figure 5 300 ns
t
d(I/O-CS)
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note10)
9 µs
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (V
ref +
– V
ref –
); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).
10. Any transitions of CS
are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425 µs) after the transition.