Datasheet

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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TLC1542I , , TLC1542M , , TLC1542Q
TLC1542C , TLC1543C , TLC1543I , TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
, see
(2)
Supply voltage range -0.5 V to 6.5 V
V
I
Input voltage range -0.3 V to V
CC
+ 0.3 V
V
O
Output voltage range -0.3 V to V
CC
+ 0.3 V
V
ref+
Positive reference voltage V
CC
+ 0.1 V
V
ref-
Negative reference voltage -0.1 V
Peak input current (any input) ± 20 mA
Peak total input current (all inputs) ± 30 mA
TLC1542C, TLC1543C 0 ° C to 70 ° C
TLC1542I, TLC1543I -40 ° C to 85 ° C
T
A
Operating free-air temperature range
TLC1542Q, TLC1543Q -40 ° C to 125 ° C
TLC1542M -55 ° C to 125 ° C
T
stg
Storage temperature range, -65 ° C to 150 ° C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
ref+
, see
(1)
Positive reference voltage V
CC
V
V
ref-
, see
(1)
Negative reference voltage 0 V
V
CC
+0.
V
ref+
-V
ref-
, see
(1)
Differential reference voltage 2.5 V
CC
V
2
Analog input voltage ,see
(1)
0 V
CC
V
V
IH
High-level control input voltage V
CC
= 4.5 V to 5.5 V 2 V
V
IL
Low-level control input voltage V
CC
= 4.5 V to 5.5 V 0.8 V
Setup time, address bits at data input before I/O
t
su(A)
, see Figure 4 100 ns
CLOCK ↑
t
h(A)
, see Figure 4 Hold time, address bits after I/O CLOCK ↑ 0 ns
t
h(CS)
, see Figure 5 Hold time, CS low after last I/O CLOCK ↓ 0 ns
t
su(CS)
, see
(2)
and Setup time, CS low before clocking in first
1.425 µ s
Figure 5 address bit
Clock frequency at I/O CLOCK, see
(3)
0 2.1 MHz
t
wH(I/O)
Pulse duration, I/O CLOCK high, 190 ns
t
wL(I/O)
Pulse duration, I/O CLOCK low, 190 ns
t
t(I/O)
, see
(4)
and
Transition time, I/O CLOCK, 1 µ s
Figure 6
t
t(CS)
Transition time, ADDRESS and CS, 10 µ s
(1) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to
REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
ref+
- V
ref-
); however, the
electrical specifications are no longer applicable.
(2) To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
(3) For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge ( ≤ 2 V) at least 1 I/O CLOCK rising edge ( ≥ 2 V) must occur within 9.5
µ s.
(4) This is the time required for the clock input signal to fall from V
IH
min to V
IL
max or to rise from V
IL
max to V
IH
min. In the vicinity of normal
room temperature, the devices function with input clock transition time as slow as 1 µ s for remote data-acquisition applications where
the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
8
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