Datasheet

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TIMING DIAGRAMS
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
InitializeInitialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Hi-Z State
1 2 3 4 5 6 7 8 9 10 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
(see Note A)
EOC
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Low Level
1 2 3 4 5 6 7 8 9 10 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
(see Note A)
Must be High on Power Up
TLC1542I , , TLC1542M , , TLC1542Q
TLC1542C , TLC1543C , TLC1543I , TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
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