Datasheet

TLC1541
10-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.5 V
Positive reference voltage, V
ref+
(see Note 2) 2.5 V
CC
V
CC
+0.1 V
Negative reference voltage, V
ref–
(see Note 2) –0.1 0 2.5 V
Differential reference voltage, V
ref+
– V
ref–
(see Note 2) 1 V
CC
V
CC
+0.2 V
Analog input voltage (see Note 2) 0 V
CC
V
High-level control input voltage, V
IH
2 V
Low-level control input voltage, V
IL
0.8 V
Input/output clock frequency, f
clock(I/O)
0 1.1 MHz
System clock frequency, f
clock(SYS)
f
clock(I/O)
2.1 MHz
Setup time, address bits before I/O CLOCK↑, t
su(A)
400 ns
Hold time, address bits after I/O CLOCK↑, t
h(A)
0 ns
Setup time, CS low before clocking in first address bit, t
su(CS)
(see Note 3 and Operating Sequence)
3
System
clock
cycles
Pulse duration, CS high during conversion, t
wH(CS)
(see Operating Sequence) 44
System
clock
cycles
Pulse duration, SYSTEM CLOCK high, t
wH(SYS)
210 ns
Pulse duration, SYSTEM CLOCK low, t
wL(SYS)
190 ns
Pulse duration, I/O CLOCK high, t
wH(I/O)
404 ns
Pulse duration, I/O CLOCK low, t
wL(I/O)
404 ns
System
f
clock(SYS)
≤ 1048 kHz 30
ns
Clock transition time (see Note 4)
S
y
stem
f
clock(SYS)
> 1048 kHz 20
ns
Clock
transition
time
(see
Note
4)
I/O
f
clock(I/O)
≤ 525 kHz 100
ns
I/O
f
clock(I/O)
> 525 kHz 40
ns
O
p
erating free-air tem
p
erature T
A
C suffix 0 70
°
C
O erating
free
-
air
tem erature
,
T
A
I suffix –40 85
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage.
Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after
a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in
an address until the minimum chip select setup time elapses.
4. The amount of time required for the clock input signal to fall from V
IH
min to V
IL
max or to rise from V
IL
max to V
IH
min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.