Datasheet

TLC1514, TLC1518
5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS252 – DECEMBER 1999
20
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (continued)
MIN NOM MAX UNIT
Transition time, for FS, SCLK, SDI, t
t(CLK)
0.5 SCLK
Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active),
t
su(CS-SCLK)
0.5 SCLK
Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),
t
h(SCLK-CS)
5 ns
Delay time, delay from CS falling edge to FS rising edge, t
d(CSL-FSH)
0.5 7 SCLKs
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), t
d(SCLK16F-CSH)
0.5 SCLKs
Setup time, FS rising edge before SCLK falling edge, t
su(FSH-SCLKF)
0.5 SCLKs
Hold time, FS hold high after SCLK falling edge, t
h(FSH-SCLKF)
0.5 SCLKs
Pulse width, CS high time, t
wH(CS)
100 ns
SCLK cycle time, V
CC
= 2.7 V to 3.6V, t
c(SCLK)
67 ns
SCLK cycle time, V
CC
= 4.5 V to 5.5V, t
c(SCLK)
50 ns
Pulse width, SCLK low time, t
wL(SCLK)
20 30 ns
Pulse width, SCLK high time, t
wH(SCLK)
20 30 ns
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),
t
su(DI-SCLK)
25 ns
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),
t
h(DI-SCLK)
5 ns
Delay time, delay from CS falling edge to SDO valid, t
d(CSL-DOV)
1 25 ns
Delay time, delay from FS falling edge to SDO valid, t
d(FSL-DOV)
1 25 ns
Delay time, delay from SCLK rising edge (FS is active) or SCLK falling edge (FS=1) SDO valid, t
d(CLK-DOV)
1 25 ns
Delay time, delay from CS rising edge to SDO 3-stated, t
d(CSH-DOZ)
1 25 ns
Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC falling
edge, t
d(CLK-EOCL)
1 25 ns
Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, t
d(EOCH-DOZ)
1 50 ns
Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLK
to INT falling edge (when FS active), t
d(SCLK-INTL)
3.5 µs
Delay time, delay from CS falling edge to INT rising edge, t
d(CSL-INTH)
1 50 ns
Delay time, delay from CS rising edge to CSTART falling edge, t
d(CSH-CSTARTL)
100 ns
Delay time, delay from CSTART rising edge to EOC falling edge, t
d(CSTARTH-EOCL)
1 50 ns
Pulse width, CSTART low time, t
wL
(CSTART) 0.8 µs
Delay time, delay from CS rising edge to EOC rising edge, t
d(CSH-EOCH)
1 50 ns
Delay time, delay from CSTART rising edge to CSTART falling edge, t
d(CSTARTH-CSTARTL)
3.6 µs
Delay time, delay from CSTART rising edge to INT falling edge, t
d(CSTARTH-INTL)
3.5 µs
Operating free-air temperature, T
A
TLC1514I/TLC1518I –40 85 C
NOTE 2: This is the time required for the clock input signal to fall from V
IH
max or to rise from V
IL
max to V
IH
min. In the vicinity of normal room
temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the
sensor and A/D converter are placed several feet away from the controlling microprocessor.