Datasheet

C
LOAD
R
F
Input
Output
R
G
R
NULL
_
+
V
OO
V
IO
1
R
F
R
G
I
IB
R
S
1
R
F
R
G
I
IB–
R
F
+
V
I
+
R
G
R
S
R
F
I
IB–
V
O
I
IB+
=
(
)
)
(
±
+
(
)
)
(
±
+ +
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011 www.ti.com
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
NULL
) with the output of the amplifier, as
shown in Figure 47. A minimum value of 20 Ω should work well for most applications.
Figure 47. Driving a Capacitive Load
Offset Voltage
The output offset voltage, (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 48. Output Offset Voltage Model
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