Datasheet

Design Procedures
2-7
Design Procedure
This information is enough to calculate the required compensation values.
Figure 2–1 shows the power stage gain and phase plots.
Figure 2–1. Power Stage Response
10 10
2
10
3
10
4
10
5
10
0
–20
–30
20
40
FREQUENCY RESPONSE
50
30
–10
–180
–225
–315
–360
–135
–45
0
–90
–270
Gain – dB (Solid)
Frequency – Hz
Phase – Degrees (Dashed)
Figure 2–2 shows the required error amplifier compensation response.
Figure 2–2. Required Compensation Response
10 10
2
10
3
10
4
20
15
0
–5
25
35
BODE PLOT
40
30
5
10
–10
–70
–90
30
70
90
50
–50
Gain – dB (Solid)
Frequency – Hz
Phase – Degrees (Dashed)
10
–30
10
5
This response can be met with the following:
A pole at zero to give high dc gain
Two zeroes at 1.87 kHz to cancel the LC poles
A pole at 26.8 kHz to cancel the ESR zero
A final pole to roll off high-frequency gain above 100 kHz