Datasheet

TL441
LOGARITHMIC AMPLIFIER
SLVS328 – OCTOBER 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional logic diagram (one half)
–15 dB
–15 dB
Log
Log
Log
Log
Σ
Y (Z)
Y
(Z)
A1
(B1)
C
A2
(C
B2
)
C
A2′
(C
B2′
)
A2
(B2)
Y ∝ log A1 + log A2; Z ∝ log B1 + log B2 where: A1, A2, B1, and B2 are in dBV, 0 dBV = 1 V.
C
A2
, C
A2′
, C
B2
, and C
B2′
are detector compensation inputs.
schematic
V
CC +
Y
Y
A2
A1
C
A2′
C
A2
V
CC –
8
6
5
7
4
3
1
2
10
11
9
12
13
14
15
Z
Z
B2
B1
GND
C
B2′
C
B2