Datasheet

TL16CP754C, TL16C754C

SLLS644G –DECEMBER 2007– REVISED MAY 2011

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Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17

shows interrupt identification register bit settings.

Table 17. Interrupt Identification Register (IIR) Bit

Settings

BIT NO. BIT SETTINGS

0 = An interrupt is pending

1 = No interrupt is pending

3:1 3-Bit encoded interrupt. See Table 16.

4 1 = Xoff/Special character has been detected.

5 CTS/RTS low to high change of state

7:6 Mirror the contents of FCR[0]

The interrupt priority list is illustrated in Table 18.

Table 18. Interrupt Priority List

PRIORITY

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INTERRUPT SOURCE

LEVEL

1 0 0 0 1 1 0 Receiver line status error

2 0 0 1 1 0 0 Receiver timeout interrupt

2 0 0 0 1 0 0 RHR interrupt

3 0 0 0 0 1 0 THR interrupt

4 0 0 1 0 0 0 Modem interrupt

5 0 1 0 0 0 0 Received Xoff signal/special character

6 1 0 0 0 0 0 CTS, RTS change of state from active (low) to inactive (high)

Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the enhanced feature

Table 19. Enhanced Feature Register (EFR) Bit Settings

BIT NO. BIT SETTINGS

3:0 Combinations of software flow control can be selected by programming bit 3−bit 0. See Table 1.

Enhanced functions enable bit.

0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5].

1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write

enable.

0 = Normal operation

5 1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is

transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.

RTS flow control enable bit

0 = Normal operation

1 = RTS flow control is enabled i.e., RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is reached,

and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.

CTS flow control enable bit

7 0 = Normal operation

1 = CTS flow control is enabled i.e., transmission is halted when a high signal is detected on the CTS pin.