Datasheet

TL16CP754C, TL16C754C
www.ti.com SLLS644G –DECEMBER 2007– REVISED MAY 2011
Table 10. '754C Internal Registers
(1) (2)
SPECIAL READ/
ADDR REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CONSIDERATIONS WRITE
000 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 Read
000 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 Write
CTS RTS Xoff Modem Rx line THR Rx data
Sleep Read/
001 IER interrupt interrupt interrupt status status empty available
mode write
enable enable enable interrupt interrupt interrupt interrupt
LCR[7] = 0
DMA
Rx trigger Rx trigger TX trigger TX trigger Resets Resets Rx Enables
010 FCR mode Write
level level level level Tx FIFO FIFO FIFOs
select
Interrupt Interrupt Interrupt
Interrupt
010 IIR FCR(0) FCR(0) CTS, RTS Xoff priority Bit priority priority Bit Read
status
2 Bit 1 0
DLAB and
Break Parity type Parity No. of Word Word Read/
None 011 LCR EFR Sets parity
control bit select enable stop bits length length write
enable
1× or 4× TCR and Enable IRQ FIFORdy Read/
100 MCR Xon any RTS DTR
clock TLR enable loopback enable Enable write
Error in Rx THR and THR Break Framing Parity Overrun Data in
101 LSR Read
LCR[7:0] ≠
FIFO TSR empty empty interrupt error error error receiver
1011 1111
110 MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS Read
Read/
111 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
Read/
000 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
LCR[7] = 1
Read/
001 DLH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
write
Read/
LCR[7:0] = 100 010 AFR DLY2 DLY1 DLY0 RCVEN 485LG 485RN IREN CONC
write
Special Enable S/W flow S/W flow S/W flow S/W flow
Read/
010 EFR Auto-CTS Auto-RTS character enhanced- control Bit control control Bit control Bit
write
detect functions 3 Bit 2 1 0
Read/
100 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
LCR[7:0] =
Read/
1011 1111 101 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
Read/
110 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
Read/
111 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
Read/
110 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
EFR[4] = 1 and
MCR[6] = 1
Read/
111 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0
write
MCR[4] = 0 and RX FIFO RX FIFO RX FIFO RX FIFO TX FIFO TX FIFO TX FIFO TX FIFO
111 FIFORdy Read
MCR[2] = 1 D status C status B status A status D status C status B status A status
(1) Bits represented by shaded cells can only be modified if EFR[4] is enabled, i.e., if enhanced functions are enabled.
(2) Refer to the notes under Table 9 for more register access information.
Receiver Holding Register (RHR)
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The
RHR is actually a 64-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel
data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled,
location zero of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RHR also
stores the error status bits associated with each character.
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