Datasheet

TL16C752C
SLLS646A –MARCH 2008–REVISED AUGUST 2009 .................................................................................................................................................... www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME
PFB RHB
GND 17 12 Pwr Power signal and power ground
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-D.
INTA−D are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt
INTA, INTB, 30, 29 20, 19 O enable register (IER) and when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or when a modem
status flag is detected. INTA−D are in the high-impedance state after reset.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal
IOR 19 13 I register defined by address bits A0–A2 onto the TL16C752C data bus (D0–D7) for
access by an external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the
IOW 15 11 I data bus (D0–D7) from the external CPU to an internal register that is defined by
address bits A0–A2.
12, 24
NC No internal connection
35, 37
User defined outputs. This function is associated with individual channels A and B. The
state of these pins is defined by the user through the software settings of the MCR
register, bit 3. INTA-B are set to active mode and OP to a logic 0 when the MCR-3 is set
OPA, OPB 32, 9 O
to a logic 1. INTA-B are set to the 3-state mode and OP to a logic 1 when MCR-3 is set
to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins
is high after reset.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter
RESET 36 24 I output and the receiver input are disabled during reset time. See TL16C752C external
reset conditions for initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A
and B. A logic low on these pins indicates the modem has received a ringing signal from
RIA, RIB, 41, 21 I the telephone line. A low-to-high transition on these input pins generates a modem
status interrupt, if enabled. The state of these inputs is reflected in the modem status
register (MSR).
Request to send (active low). These outputs are associated with individual UART
channels A through D. A low on the RTS pins indicates the transmitter has data ready
and waiting to send. Writing a 1 in the modem control register (MCR[1]) sets these pins
RTSA, RTSB, 33, 22 21, 14 O
to low, indicating data is available. After a reset, these pins are set to 1. These pins only
affect the transmit and receive operation when auto-RTS function is enabled through the
enhanced feature register (EFR[6]), for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to
the TL16C752C. During the local loopback mode, these RX input pins are disabled and
RXA, RXB, 5, 4 4, 3 I TX data is internally connected to the UART RX input internally. During normal mode,
RXn should be held high when no data is being received. These outputs also can be
used in IrDA mode. See the IrDA mode section for more information.
Receive ready (active low). RXRDYA and RXRDYB go low when the trigger level has
RXRDYA,
31, 18 O been reached or a timeout interrupt occurs. They go high when the RX FIFO is empty or
RXRDYB
there is an error in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data
TXA, TXB, 7, 8 5, 6 O from the TL16C752C. During the local loopback mode, the TX input pin is disabled and
TX data is internally connected to the UART RX input.
TXRDYA, Transmit ready (active low). TXRDYA and TXRDYB go low when there are a trigger
43, 6 O
TXRDYB level number of spares available. They go high when the TX buffer is full.
V
CC
42 26 Pwr Power supply inputs
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock
input. A crystal can be connected between XTAL1 and XTAL2 to form an internal
XTAL1 13 9 I
oscillator circuit (see Figure 10). Alternatively, an external clock can be connected to
XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a
XTAL2 14 10 O
crystal oscillator output or buffered clock output.
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