Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
23
24
22
21
20
19
18
17
D6
D7
RXB
RXA
TXA
TXB
CSA
CSB
RESET
DTRB
DTRA
RTSA
INTA
INTB
A0
A1
32
31
30
29
28
27
26
25
D5
D4
D3
D2
D1
D0
V
CC
CTSA
XTAL1
XTAL2
IOW
GND
IOR
RTSB
CTSB
A2
TL16C752CRHB
TL16C752C
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.................................................................................................................................................... SLLS646A –MARCH 2008–REVISED AUGUST 2009
RHB PACKAGE
(TOP VIEW)
NOTE: The 32-pin RHB package does not provide access to DSRA, DSRB, RIA, RIB, CDA, CDB inputs or OPA, OPB,
RXRDYA, RXRDYB, TXRDYA outputs.
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTION
NAME
PFB RHB
Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register
A0 28 18 I
Address Map.
Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register
A1 27 17 I
Address Map.
Address bit 2 select. Internal registers address selection. Refer to Table 9 for Register
A2 26 16 I
Address Map.
Carrier detect (active low). These inputs are associated with individual UART channels A
CDA, CDB, 40, 16 I through B. A low on these pins indicates that a carrier has been detected by the modem
for that channel.
Chip select A and B (active low). These pins enable data transfers between the user
CSA, CSB, 10, 11 7, 8 I CPU and the TL16C752C for the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A
and B. A low on the CTS pins indicates the modem or data set is ready to accept
CTSA, CTSB, 38, 23 25, 15 I transmit data from the TL16C752C. Status can be checked by reading MSR[4]. These
pins only affect the transmit and receive operations when auto CTS function is enabled
through the enhanced feature register (EFR[7]), for hardware flow control operation.
Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring
D0–D4, 44–48, 27–31
I/O information to or from the controlling CPU. D0 is the least significant bit and the first data
D5–D7 1–3 32, 1, 2
bit in a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels
DSRA, DSRB, 39, 20 I A through B. A low on these pins indicates the modem or data set is powered on and is
ready for data exchange with the UART.
Data terminal ready (active low). These outputs are associated with individual UART
channels A through B. A low on these pins indicates that the TL16C752C is powered on
and ready. These pins can be controlled through the modem control register. Writing a 1
DTRA, DTRB, 34, 35 22, 23 O
to MCR[0] sets the DTR output to low, enabling the modem. The output of these pins is
high after writing a 0 to MCR[0], or after a reset. These pins can also be used in the
RS-485 mode to control an external RS-485 driver or transceiver.
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