Datasheet

16-BaudRateClock
TX(A B)–
INT(A B)–
IOW
Start
Bit
Parity
Bit
Stop
Bit
Next
Data
Start
Bit
DataBits(5–8)
T27d
t
28d
D0
D7D1 D4D2
D5D3 D6
Active
Transmitter
NotReady
Byte1
Active
TransmitterReady
TX(A B)–
IOW
D0 D7–
TXRDY (A B)–
TXRDY
TL16C752C
www.ti.com .................................................................................................................................................... SLLS646A –MARCH 2008–REVISED AUGUST 2009
Figure 21. Transmit Timing
Figure 22. Transmit Ready Timing in None FIFO Mode
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