Datasheet

Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate 16)X
1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset
4 when CLKSEL = high during reset, or MCR[7] is set to 1 after reset
prescaler =
Prescaler Logic
(Divide By 1)
Prescaler Logic
(Divide By 4)
Internal
Oscillator
Logic
Bandrate
Generator
Logic
XTAL1
XTAL2
Internal
Bandrate Clock
For Transmitter
and Receiver
MCR[7] = 0
MCR[7] = 1
Input Clock
Reference
Clock
TL16C752C
www.ti.com .................................................................................................................................................... SLLS646A –MARCH 2008–REVISED AUGUST 2009
Programmable Baud Rate Generator
The TL16C752C UART contains a programmable baud generator that divides reference clock by a divisor in the
range between 1 and (216−1). The output frequency of the baud rate generator is 16× the baud rate. An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in the following. The
formula for the divisor is:
Where
Figure 9 shows the internal prescaler and baud rate generator circuitry.
Figure 9. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as
no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and
receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
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