Datasheet
TL16C752C
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.................................................................................................................................................... SLLS646A –MARCH 2008–REVISED AUGUST 2009
Table 2. Register Reset Functions
(1)
RESET
REGISTER RESET STATE
CONTROL
Interrupt enable register RESET All bits cleared
Interrupt identification register RESET Bit 0 is set. All other bits cleared.
FIFO control register RESET All bits cleared
Line control register RESET Reset to 00011101 (1D hex).
Modem control register RESET All bits cleared
Line status register RESET Bits 5 and 6 set. All other bits cleared.
Modem status register RESET Bits 0–3 cleared. Bits 4–7 input signals.
Enhanced feature register RESET All bits cleared
Receiver holding register RESET Pointer logic cleared
Transmitter holding register RESET Pointer logic cleared
Transmission control register RESET All bits cleared
Trigger level register RESET All bits cleared
Alternate function register RESET All bits (except AFR4) cleared; AFR4 set
(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,
i.e., they hold their initialization values during reset.
Table 3 summarizes the state of outputs after reset.
Table 3. Signal Reset Functions
SIGNAL RESET CONTROL RESET STATE
TX RESET High
RTS RESET High
DTR RESET High
RXRDYA–B RESET High
TXRDYA–B RESET Low
Interrupts
The TL16C752C UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to
an interrupt generation. The IER also can disable the interrupt system by clearing bits 0−3, 5−7. When an
interrupt is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
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